1. Field of the Invention
The present invention relates to data processing and specifically to data processing in a transmitter/receiver for data transmitted over multiple lanes.
2. Description of Related Art
Various interconnection systems based on the OSI (Open Systems Interconnection) Reference Model have been standardized as multi-vendor interconnection international standard protocol systems. In recent years, IEEE (Institute of Electrical and Electronics Engineers) 802.3 in charge of standardizing Ethernet (registered trademark) that is the sublayer MAC (Media Access Control) of the second layer (Data Link Layer) of the OSI Reference Model has standardized 10 Gigabit Ethernet (10 GbE) ten times as fast as Gigabit. Ethernet into IEEE 802.3ae. 10 GbE is being introduced in earnest into LANs (Local Area Networks)/MANs (Metropolitan Area Networks) as well as the backbones of communication carriers.
10 GbE uses the same MAC as conventional Ethernet and inherits the conventional frame format according to its basic concept of using as much of existing technology as possible as long as usable, thereby suppressing development costs and period.
As to the physical layer, 10 GbE has a specification called PHY on the WAN (Wide Area Network) side (WAN PHY), which conventional Ethernet does not have, and as to PHY on the LAN side (LAN PHY), a modified version of that of conventional Ethernet is used.
As to the LAN PHY of 10 GbE, there are several segmented specifications. Here, description will be made taking 10 GBASE-R PHY as an example.
FIG. 10 shows the structure of 10 GBASE-R PHY together with the OSI Reference Model of seven layers. As shown in the figure, 10 GBASE-R PHY consists of RS (Reconciliation Sublayer), XGMII (10 Gigabit Media Independent Interface), PCS (Physical Coding Sublayer), PMA (Physical Medium Attachment), PMD (Physical Medium Dependent), and MDI (Medium Dependent Interface).
RS is a part in between MAC and XGMII that performs signal conversion and is connected to PCS via XGMII.
XGMII deals with a rate of 10 Gbps and functions as the interface between RS and PCS.
PCS is in charge of the coding/decoding and scrambling of data, and 10 GBASE-R PHY uses a method called “64B/66B conversion” specified in IEEE 802.3ae-2002 Clause 49 for coding/decoding. The 64B/66B conversion is a method that expresses 64-bit data in a 66-bit symbol when coding, which converts 64-bit data to a 66-bit expression. When decoding, the opposite of the conversion in coding is performed.
PMA is a serializer/deserializer (hereinafter called a SerDes) that serializes data when transmitting and parallelizes when receiving. Specifically, when transmitting, PMA converts 16-bit parallel data into a serial data stream and passes it to PMD, and when receiving, PMA parallelizes a serial data stream from PMD into 16-bit parallel data.
PMD performs photoelectric signal conversion and is connected to a physical medium via MDI. MDI corresponds to an end connection of an Ethernet cable (an optical cable for 10 GbE).
As shown in FIG. 49-5 of IEEE 802.3ae-2002 Clause 49, PCS performs data passing with XGMII on an 8-byte, i.e. 64-bit, unit basis. Here, XGMII is an interface having a 32-bit width for data. Hence, in transmission, after receiving two cycles worth of data from XGMII, PCS performs 64B/66B conversion, and in reception, PCS divides 64-bit data into two parts, outputting one at a time to XGMII.
Here, the 64B/66B conversion by PCS will be described with reference to FIGS. 11 to 17 taking the transmission as an example.
As shown in FIG. 11, in transmission, signals flow from XGMII 10 to a 64B/66B converter 22 of PCS 20 to a scrambling section 24. A signal flowing through XGMII 10, a signal taken in by the 64B/66B converter 22, and a signal output by the 64B/66B converter 22 are signal A, signal B, and signal C respectively.
FIG. 12 shows the format of signal A flowing through XGMII 10. Signal A includes a control signal TXC[3:0] and a data signal TXD[31:0], which each are transmitted over four lanes: lane 0 to lane 3. As shown in the figure, the data signal TXD[31:0] starts with a frame start code /S/ and ends with a frame end code /T/. While the start code /S/ is always located on lane 0, the lane where the end code /T/ is located differs depending on the length of the frame. As a signal of XGMII, there is a clock signal TX_CLK (not shown) as well as the control signal TXC[3:0] and data signal TXD[31:0]. The control signal TXC[3:0] and data signal TXD[31:0] change synchronously with the rise and fall edges of this clock signal TX_CLK.
The data signal is transmitted on the basis of one byte of data per cycle over each lane (indicated by a small rectangle in the figure). Data on the four lanes in the same cycle together, hatched in FIG. 12, are called a “column”. As mentioned above, because PCS 20 takes in 8 bytes of data at a time, the boundary between each 8 bytes of data is called an “8-byte boundary”. PCS 20 takes in two columns present between two adjacent 8-byte boundaries at a time. Hereinafter, two columns present between two adjacent 8-byte boundaries together are called a “block”.
The format of signal B taken in by the 64B/66B converter 22 of PCS 20 and the format of signal C into which the 64B/66B converter 22 converts the taken-in signal B are shown in FIG. 13.
As shown in FIG. 13, the 64B/66B converter 22 takes in a block (4 bytes×2) consisting of two columns of the data signal TXD in signal A and two columns (4 bits×2) of the control signal TXC transmitted in the same cycles as these two columns to obtain tx_raw[71:0] as the signal B. The tx_raw[71:0] has first 8 bits as the control portion and subsequent 8 bytes, i.e., 64 bits as the data portion, amounting to a total of 72 bits.
The 64B/66B converter 22 performs 64B/66B conversion on the tx_raw[71:0] so as to code it into tx_coded[65:0] as signal C, which is output to the scrambling section 24.
The tx_coded[65:0] has first 2 bits as the sync head for synchronizing and subsequent 64 bits as the data portion, amounting to a total of 66 bits.
FIG. 14 is a diagram of the process by the 64B/66B converter 22, focusing on only the data signal. As shown in the figure, two columns of data from XGMII 10 are encoded by the 64B/66B conversion into 64 bits of data. Note that although data is different in value before and after the 64B/66B conversion, they are both denoted as “D” for convenience of expression.
Here, the case where there is an error code in the data signal TXD from XGMII will be described. FIG. 15 shows an example where an error code /E/ is included in the data signal TXD. The bit pattern of the error code /E/ in XGMII is FEh in hexadecimal, but a byte in the data signal TXD is not interpreted as the error code if the value of the byte is FEh, without any other condition. If the logic value on the same lane of the control signal TXC (TXC[1] in FIG. 15) at the same cycle as the byte is a Hi (high) with the value of the byte being FEh, the byte is interpreted as the error code.
When 64B/66B-converting data containing the error code as shown in FIG. 15, the 64B/66B converter 22 performs a process called error expansion. FIGS. 16, 17 show schematically the error expansion.
If the error code /E/ is included in a block of the data signal TXD as shown in FIG. 16, a total of 8 bytes of two columns included in this block are all made to be an error code by the error expansion during the 64B/66B conversion. Note that although the bit pattern of the error code after the 64B/66B conversion is 1Eh in hexadecimal, it is denoted as /E/, which is the same as the error code before the 64B/66B conversion, for convenience of expression.
FIG. 16 shows an example where the error code /E/ is included in the one adjacent to the preceding 8-byte boundary of the two columns in a block of the data signal TXD. FIG. 17 shows an example where the error code /E/ is included in the one adjacent to the subsequent 8-byte boundary of the two columns in a block of the data signal TXD. As shown in FIG. 17, also in this case, the 8 bytes of the block including the error code /E/ are all replaced with the error code by the error expansion.
This error expansion is performed likewise on the receiver side as well, not being limited to the transmitter side. This has the advantage that other devices and process blocks can be reliably notified of the error if an error exists in a frame being transmitted or received.
Meanwhile, in communication systems, error analysis or the performance test of transmitters/receivers may be performed. Accordingly various devices are implemented to better perform the analysis or the test.
Japanese Unexamined Patent Application Publication No. 2005-130177 (Reference 1) discloses a technique where a capture apparatus analyzes data input from a transmission line and divides the data into lanes of data to be displayed on a byte-unit basis. According to this technique, data is divided into lanes of data to be displayed, and hence it is expected to be easy to perform error analysis.
Japanese Unexamined Patent Application Publication No. 2005-184801 (Reference 2) discloses a technique where an error area is extended intentionally by a testing apparatus that corresponds to a transmitter for frames. This technique, expecting that in the 64B/66B conversion the error code /E/ is expanded to 8 bytes, replaces the 12 bytes of a total of three columns, a column including the error code /E/ and its preceding and following columns, with the error code /E/ and then performs FCS computation. By this means, a frame including no FCS error but the error codes /E/ and frames including no error code can be mixed and given to a test subject apparatus, and thus it becomes easy to confirm whether the subject apparatus can discard only the frame including the error codes.